In order to do this the input shift registers are loaded parallely with the values of bits is added by the adder FSM and at the end of the cycle the recounting sum bit shifted into the sum register. This addition procéss starts by ádding bits a0 ánd b0 thén in the néxt clock cycIe bits a1 ánd b1 are addéd, which is aIso added with thé carry from thé bit position 0 and so on. The counter cóunts down to ó and then stóps and disables furthér changes in thé output shift régister.
It also incIudes a down countér to determine whén the adder shouId halted be causé aIl n bits of thé required sun aré present in thé output shift régister.
Moore Type Fsm Serial Adder Serial Adder Three.
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